The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8422319 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 16, 2013

Filed:

May. 30, 2011
Applicants:

Srinivas Sriadibhatla, Karnataka, IN;

Curtis Matheson Webster, San Ramon, CA (US);

Inventors:

Srinivas Sriadibhatla, Karnataka, IN;

Curtis Matheson Webster, San Ramon, CA (US);

Assignee:

LSI Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method for gate training in a memory system is disclosed. In one embodiment, in a method for calibrating read data strobe gating, a first read command is issued to a memory module. A first DQS gate signal is issued before the beginning of the preamble of a first DQS signal received from the memory module that corresponds to the first read command. A second read command is issued to the memory module such that the preamble of a second DQS signal received from the memory module that corresponds to the second read command is adjacent to the postamble of the first DQS signal. Then, a second DQS gate signal is issued at a preset time after the first DQS gate signal. The second DQS signal is sampled repeatedly to locate the preamble of the second DQS signal.


Find Patent Forward Citations

Sriadibhatla, Srinivas. (2013). System and method for gate training in a memory system (U.S. Patent No. 8422319). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8422319

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