The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2013

Filed:

Oct. 28, 2011
Applicants:

Stefan Buettner, Sindelfingen, DE;

David A. Hrusecky, Cedar Park, TX (US);

Werner Juchmes, Boeblingen, DE;

Wolfgang Penth, Holzgerlingen, DE;

Rolf Sautter, Bondorf, DE;

Inventors:

Stefan Buettner, Sindelfingen, DE;

David A. Hrusecky, Cedar Park, TX (US);

Werner Juchmes, Boeblingen, DE;

Wolfgang Penth, Holzgerlingen, DE;

Rolf Sautter, Bondorf, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper part and a lower part of the global bit line. The selection circuitry is adapted to receive an early set prediction signal and to connect the upper part of the global bit line to the lower part of the global bit line based on the early set prediction signal. The early set prediction signal indicates whether a set of memory cells, which include the memory cell, is being read. The circuit also includes a N:1 multiplexer connected to the lower part of the global bit line to receive the lower part of the global bit line as input.


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