The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2013
Filed:
Mar. 10, 2011
Suguru Kawabata, Osaka, JP;
Shinobu Yamazaki, Osaka, JP;
Yoshiji Ohta, Osaka, JP;
Kazuya Ishihara, Osaka, JP;
Nobuyoshi Awaya, Osaka, JP;
Akio Kitagawa, Kanazawa, JP;
Kazuya Nakayama, Kanazawa, JP;
Suguru Kawabata, Osaka, JP;
Shinobu Yamazaki, Osaka, JP;
Yoshiji Ohta, Osaka, JP;
Kazuya Ishihara, Osaka, JP;
Nobuyoshi Awaya, Osaka, JP;
Akio Kitagawa, Kanazawa, JP;
Kazuya Nakayama, Kanazawa, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
National University Corporation Kanazawa University, Ishikawa, JP;
Abstract
A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.