The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2013
Filed:
Sep. 02, 2011
Alfred Yeung, Fremont, CA (US);
Hamid Partovi, Los Altos, CA (US);
Luca Ravezzi, San Francisco, CA (US);
John Ngai, Boxborough, MA (US);
Alfred Yeung, Fremont, CA (US);
Hamid Partovi, Los Altos, CA (US);
Luca Ravezzi, San Francisco, CA (US);
John Ngai, Boxborough, MA (US);
Applied Micro Circuits Corporation, Sunnyvale, CA (US);
Abstract
A hazard-free minimal-latency flip-flop (HFML-FF) is provided. A master latch includes an input to accept a Dsignal, an input to accept a clock signal, an input to accept an inverted shadow-Dsignal, and an output to supply a Dsignal. The master latch has an input to accept a shadow-Dsignal, an input to accept the clock signal, and an output to supply a shadow-Dsignal and the inverted shadow-Dsignal. The slave latch has an input to accept the Dsignal, an input to accept the clock signal, an input to accept an inverted shadow-Q signal, and an output to supply a Q signal. The slave latch has an input to accept either the Dsignal or the shadow-Dsignal, an input to accept the clock signal, and an output to supply a shadow-Q signal and the inverted shadow-Q signal. The design may use clocked inverters or pass gates.