The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8421175 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 16, 2013

Filed:

Sep. 10, 2009
Applicant:

Robert Nicol, Lanarkshire, GB;

Inventor:

Robert Nicol, Lanarkshire, GB;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0232 (2006.01);
U.S. Cl.
CPC ...
Abstract

A wafer level packaged integrated circuit includes an array of contacts, a silicon layer and a glass layer. The silicon and glass layers are bonded together to form a bonding material layer therebetween. The bonding material layer includes gaps between the silicon layer and the glass layer at areas where no bonding material is present. An array of contacts is adjacent the semiconductor layer on a side thereof opposite the bonding layer. The wafer level packaged integrated circuit is provided with additional bonding material layer portions within the gaps and aligned with at least some of the contacts. When the wafer level packaged integrated circuit is configured as an image sensor or display having a pixel array, the additional bonding material layer portions are not used in an area of the pixel array.


Find Patent Forward Citations

Nicol, Robert. (2013). Wafer level packaged integrated circuit (U.S. Patent No. 8421175). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8421175

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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