The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2013
Filed:
Jan. 24, 2011
Yo Shimazaki, Tsurugashima, JP;
Hiroyuki Saito, Tokorozawa, JP;
Masachika Masuda, Tokorozawa, JP;
Kenji Matsumura, Iruma-Gun, JP;
Masaru Fukuchi, Saitama, JP;
Takao Ikezawa, Shinjuku-Ku, JP;
Yo Shimazaki, Tsurugashima, JP;
Hiroyuki Saito, Tokorozawa, JP;
Masachika Masuda, Tokorozawa, JP;
Kenji Matsumura, Iruma-Gun, JP;
Masaru Fukuchi, Saitama, JP;
Takao Ikezawa, Shinjuku-Ku, JP;
Dai Nippon Printing Co., Ltd., Shinjuku-Ku, JP;
Abstract
A circuit member includes a lead frame material having a die pad, a lead part to be electrically connected with a semiconductor chip, and an outer frame configured to support the die pad and the lead part. The lead frame material includes a resin sealing region. Roughened faces, each having an average roughness Ra of 0.3 μm or greater, are formed on a surface in the resin sealing region of the lead frame material. The surface of the lead frame material except for the resin sealing region is a flat and smooth face. A two-layer plated layer formed by laminating a Ni plated layer and a Pd plated layer in this order or a three-layer plated layer formed by laminating the Ni plated layer, the Pd plated layer and an Au plated layer in this order is formed on the whole surface of the lead frame material.