The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2013

Filed:

Feb. 12, 2004
Applicants:

Jay T. Young, Louisville, CO (US);

Ian L. Mcewen, Golden, CO (US);

Inventors:

Jay T. Young, Louisville, CO (US);

Ian L. McEwen, Golden, CO (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods of prioritizing untested routing resources in programmable logic devices (PLDs) to generate test suites that include a minimal number of test designs. The untested routing resources are prioritized (e.g., placed into an ordered list) based on a number of untested input or output terminals for each untested resource. The number of untested input or output terminals (whichever is larger) for each routing resource determines the minimum number of additional test designs in which the routing resource must be included. The resulting prioritization can be utilized by a router, for example, to first include in test designs those routing resources that must be included in the largest remaining number of test designs. The described prioritization methods can also be used to select one of two or more test designs that should be included in the overall test suite. In each case, the overall number of test designs is reduced.


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