The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2013
Filed:
Sep. 21, 2011
Kevin Joseph Blostic, Bentleyville, PA (US);
James Jacob Riling, Pittsburgh, PA (US);
Adam Edward Szymkowiak, Sewickley, PA (US);
Todd Anthony Delong, Ivy, VA (US);
Joseph William Reutzel, Pittsburgh, PA (US);
Anthony Pietro Mancini, Ii, Jefferson Hills, PA (US);
Kevin Joseph Blostic, Bentleyville, PA (US);
James Jacob Riling, Pittsburgh, PA (US);
Adam Edward Szymkowiak, Sewickley, PA (US);
Todd Anthony DeLong, Ivy, VA (US);
Joseph William Reutzel, Pittsburgh, PA (US);
Anthony Pietro Mancini, II, Jefferson Hills, PA (US);
Ansaldo STS USA, Inc., Pittsburgh, PA (US);
Abstract
A method of testing a target electronic device implemented in a configurable integrated circuit device includes receiving a baseline design for the target electronic device in a hardware description language, establishing a fault model for the particular configurable integrated circuit device, synthesizing the fault model in the hardware description language, embedding the synthesized fault model into the baseline design to create a modified baseline design in the hardware description language which enables one or more targeted signals to be selectively corrupted, creating a fault model enabled target device on the particular configurable integrated circuit device using the modified baseline design, performing a number of fault injection experiments on the fault model enabled target device, wherein each fault injection experiment includes causing at least one of the one or more targeted signals to be corrupted within the fault model enabled target device.