The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8418009 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 09, 2013

Filed:

May. 12, 2010
Applicant:

Tsutomu Ishida, Kawasaki, JP;

Inventor:

Tsutomu Ishida, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A computer-readable medium stores therein a program that causes a computer to execute acquiring for each chip, first delay values of paths in chips manufactured using circuit information concerning a circuit-under-test; building a function model representing a delay value of a path, based on the first delay values for the path and the circuit information; calculating a second delay value of a path included in and having the same configuration in each chip, using a built function model and the circuit information; comparing for each chip, a given calculated second delay value and the first delay value of a given path having a configuration identical to that of the path for which the given second delay value has been calculated; determining based on a comparison result, the given path to be a path that includes a delay error occurring irregularly according to chip; and outputting a determination result.


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Ishida, Tsutomu. (2013). Delay fault testing computer product, apparatus, and method (U.S. Patent No. 8418009). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8418009

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