The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2013
Filed:
Feb. 11, 2009
Hajime Akimoto, Kokubunji, JP;
Yasuharu Yatsu, Chiba, JP;
Hiroshi Kageyama, Hachioji, JP;
Noriharu Matsudate, Kujukuri, JP;
Naruhiko Kasai, Yokohama, JP;
Hajime Akimoto, Kokubunji, JP;
Yasuharu Yatsu, Chiba, JP;
Hiroshi Kageyama, Hachioji, JP;
Noriharu Matsudate, Kujukuri, JP;
Naruhiko Kasai, Yokohama, JP;
Hitachi Displays, Ltd., Chiba-ken, JP;
Panasonic Liquid Crystal Display Co., Ltd., Hyogo-ken, JP;
Abstract
The present invention realizes the reduction of cost of a display device having a touch panel. The display device having a touch panel includes a display panel, and a touch panel which is arranged on the display panel in an overlapping manner in plane. The touch panel includes a first substrate and a second substrate which are arranged to face each other with spacers sandwiched therebetween, and a first semiconductor chip which is mounted on the first substrate. The first substrate includes, on a surface side thereof which faces the second substrate, a plurality of first lines which is arranged parallel to each other in the first direction, a first chip mounting region on which the first semiconductor chip is mounted, and a plurality of first connection portions each of which is constituted of a portion of each line in the plurality of first lines, the first semiconductor chip includes a plurality of first bump electrodes which is arranged in one direction, the plurality of first connection portions are arranged in the arrangement direction of the plurality of first bump electrodes within the first-chip mounting region, and an arrangement pitch of the plurality of first bump electrodes is set larger than an arrangement pitch of the plurality of first connection portions.