The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2013

Filed:

Dec. 17, 2010
Applicants:

Mikko T. Loikkanen, Oulu, FI;

Juha O. Hauru, Pummimiehentie, FI;

Ari Kalevi Vããnãnen, Oulu, FI;

Inventors:

Mikko T. Loikkanen, Oulu, FI;

Juha O. Hauru, Pummimiehentie, FI;

Ari Kalevi Vããnãnen, Oulu, FI;

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/613 (2006.01); G05F 1/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A control circuit for controlling a DC-DC converter, with the converter including an inductor and associated switching circuitry, with the switching circuitry including a first transistor switch connected intermediate an input voltage terminal and a first terminal of the inductor, a second transistor switch connected intermediate the first terminal of the inductor and a circuit reference, a third transistor switch connected intermediate a second terminal of the inductor and an output voltage terminal and a fourth transistor switch connected intermediate the second terminal of the inductor and the circuit reference. Mode control circuitry responsive to separate buck and boost comparators and configured to cause the switching circuitry to switch among a pass phase where the first and second transistor switches are ON, a boost phase where the first and third transistors are ON and a buck phase where the second and third transistors are ON, with first selected switching periods beginning operation in the pass phase followed, in response to an output of the buck comparator, with operation in the buck phase and with second selected switching periods beginning operation in the pass phase followed, in response to an output of the boost comparator, to operation in the boost phase.


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