The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2013

Filed:

Oct. 29, 2011
Applicants:

Chang-woo OH, Suwon-si, KR;

Dong-gun Park, Seongnam-si, KR;

Dong-won Kim, Seongnam-si, KR;

Dong-uk Choi, Hwaseong-si, KR;

Kyoung-hwan Yeo, Seoul, KR;

Inventors:

Chang-Woo Oh, Suwon-si, KR;

Dong-Gun Park, Seongnam-si, KR;

Dong-Won Kim, Seongnam-si, KR;

Dong-Uk Choi, Hwaseong-si, KR;

Kyoung-Hwan Yeo, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/337 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
Abstract

A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.


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