The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2013
Filed:
Dec. 13, 2011
Jean-marc Fedeli, Saint Egreve, FR;
Guang-hua Duan, Sceaux, FR;
Delphine Marris-morini, Montrouge, FR;
Gilles Rasigade, Paris, FR;
Laurent Vivien, Vauhallan, FR;
Melissa Ziebell, Paris, FR;
Jean-Marc Fedeli, Saint Egreve, FR;
Guang-Hua Duan, Sceaux, FR;
Delphine Marris-Morini, Montrouge, FR;
Gilles Rasigade, Paris, FR;
Laurent Vivien, Vauhallan, FR;
Melissa Ziebell, Paris, FR;
Commissariat a l'Energie Atomique et aux Energies Alternatives, Paris, FR;
Alcatel Lucent, Paris, FR;
Centre National de la Recherche Scientifique, Paris, FR;
Universite Paris-SUD 11, Orsay, FR;
Abstract
In a process for fabrication of an optical slot waveguide on silicon, a thin single-crystal silicon film is deposited on a substrate covered with an insulating buried layer; a local thermal oxidation is carried out over the entire depth of the thin single-crystal silicon film in order to form an insulating oxidized strip extending along the desired path of the waveguide; an insulating or semi-insulating layer is deposited on the silicon film; two openings having vertical sidewalls are excavated over the entire thickness of this insulating or semi-insulating layer, said openings being separated by a narrow gap constituting an insulating or semi-insulating vertical wall that will be the material of the slot; single-crystal silicon is grown in the openings and right to the edges of the insulating or semi-insulating wall; and then the upper part of the silicon is etched in order to complete the geometry of the waveguide.