The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2013

Filed:

Sep. 07, 2010
Applicants:

Yasuki Tanabe, Chiba, JP;

Takashi Miyamori, Kanagawa, JP;

Shunichi Ishiwata, Chiba, JP;

Katsuyuki Kimura, Kanagawa, JP;

Keiri Nakanishi, Kanagawa, JP;

Masato Sumiyoshi, Tokyo, JP;

Ryuji Hada, Kanagawa, JP;

Inventors:

Yasuki Tanabe, Chiba, JP;

Takashi Miyamori, Kanagawa, JP;

Shunichi Ishiwata, Chiba, JP;

Katsuyuki Kimura, Kanagawa, JP;

Keiri Nakanishi, Kanagawa, JP;

Masato Sumiyoshi, Tokyo, JP;

Ryuji Hada, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
Abstract

According to an embodiment, a compiling device compiling a source program written so as to use a frame memory includes a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data processed by the process tasks. The compiling device also includes a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data and an instruction code converter configured to convert the plurality of process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes.


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