The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 2013
Filed:
Feb. 21, 2012
John P. Dubuque, Jericho, VT (US);
Eric A. Foreman, Fairfax, VT (US);
Peter A. Habitz, Hinesburg, VT (US);
Jeffrey G. Hemmett, St. George, VT (US);
Amol A. Joshi, Essex Junction, VT (US);
Christopher J. Kiegle, Jericho, VT (US);
William J. Wright, Colchester, VT (US);
Vladimir Zolotov, Putnam Valley, NY (US);
John P. Dubuque, Jericho, VT (US);
Eric A. Foreman, Fairfax, VT (US);
Peter A. Habitz, Hinesburg, VT (US);
Jeffrey G. Hemmett, St. George, VT (US);
Amol A. Joshi, Essex Junction, VT (US);
Christopher J. Kiegle, Jericho, VT (US);
William J. Wright, Colchester, VT (US);
Vladimir Zolotov, Putnam Valley, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A statistical single library that includes on-chip variation (OCV) is created for timing and power analysis of a digital chip design. Initially, library values for all cells of a digital chip design, including ranges for environmental and process parameters, are subject to a statistical model to create statistical timing for the ranges of the parameters. A statistical timing tool is applied across the ranges of the parameters to determine statistical corners for delay and input power to a subset of cells. The statistically determined delay and input power to the subset of cells is entered into the statistical single library. Each delay of each statistical corner for the subset of cells is compared with a chip sign-off statistical delay requirement of a test macro.