The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 2013
Filed:
Jan. 29, 2010
Dong Chen, Yorktown Heights, NY (US);
Matthew R. Ellavsky, Rochester, MN (US);
Ross L. Franke, Rochester, MN (US);
Alan Gara, Yorktown Heights, NY (US);
Thomas M. Gooding, Rochester, MN (US);
Rudolf A. Haring, Yorktown Heights, NY (US);
Mark J. Jeanson, Rochester, MN (US);
Gerard V. Kopcsay, Yorktown Heights, NY (US);
Thomas A. Liebsch, Sious Falls, SD (US);
Daniel Littrell, Carmel, NY (US);
Martin Ohmacht, Yorktown Heights, NY (US);
Don D. Reed, Rochester, MN (US);
Brandon E. Schenck, Rochester, MN (US);
Richard A. Swetz, Mahopac, NY (US);
Dong Chen, Yorktown Heights, NY (US);
Matthew R. Ellavsky, Rochester, MN (US);
Ross L. Franke, Rochester, MN (US);
Alan Gara, Yorktown Heights, NY (US);
Thomas M. Gooding, Rochester, MN (US);
Rudolf A. Haring, Yorktown Heights, NY (US);
Mark J. Jeanson, Rochester, MN (US);
Gerard V. Kopcsay, Yorktown Heights, NY (US);
Thomas A. Liebsch, Sious Falls, SD (US);
Daniel Littrell, Carmel, NY (US);
Martin Ohmacht, Yorktown Heights, NY (US);
Don D. Reed, Rochester, MN (US);
Brandon E. Schenck, Rochester, MN (US);
Richard A. Swetz, Mahopac, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.