The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2013

Filed:

Apr. 29, 2011
Applicants:

Valentina Nardone, Avezzano, IT;

Stefano Pucillo, Paderno d'Adda, IT;

Roberto Canegallo, Rimini, IT;

Claudio Mucci, Bologna, IT;

Massimiliano Innocenti, Urbino, IT;

Luca Perugini, Lugo di Ravenna, IT;

Inventors:

Valentina Nardone, Avezzano, IT;

Stefano Pucillo, Paderno d'Adda, IT;

Roberto Canegallo, Rimini, IT;

Claudio Mucci, Bologna, IT;

Massimiliano Innocenti, Urbino, IT;

Luca Perugini, Lugo di Ravenna, IT;

Assignee:

STMicroelectronics S.R.L., Agrate Brianza (MB), IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 7/10 (2006.01); G11C 8/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory base cell stores a bit of information implemented from a regular and compact structure made up of multiple identical and replicated base elements, on the 'sea of gates' model, in which the base element of the structure is a cell able to be configured with a minimum width in relation to the particular technology used. Such a cell includes a bistable element with an input node operatively connected to a writing data line of the memory base cell, and an output node operatively connected to a reading data line of the memory base cell. The bistable element also has a first inverter and a second inverter arranged in a feedback configuration with respect to one another between the input node and the output node of the bistable element.


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