The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 2013
Filed:
Sep. 02, 2011
Mitsuru Nakura, Osaka, JP;
Kazuya Ishihara, Osaka, JP;
Shinobu Yamazaki, Osaka, JP;
Suguru Kawabata, Osaka, JP;
Mitsuru Nakura, Osaka, JP;
Kazuya Ishihara, Osaka, JP;
Shinobu Yamazaki, Osaka, JP;
Suguru Kawabata, Osaka, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided. Further, the memory cell array is constituted of even-numbers of subbanks, and the application of the erasing voltage pulse in one subbank and the application of the programming voltage pulse in the other subbank are alternately performed.