Gate driving circuit having a shift register stage capable of pulling down gate signals of a plurality of shift register stages

Abstract

A high-reliability gate driving circuit includes a plurality of odd shift register stages and a plurality of even shift register stages. Each odd shift register stage generates a corresponding gate signal furnished to a corresponding odd gate line according to a first clock and a second clock having a phase opposite to the first clock, and further functions to pull down a gate signal of at least one even gate line or at least one odd gate line different from the corresponding odd gate line. Each even shift register stage generates a corresponding gate signal furnished to a corresponding even gate line according to a third clock and a fourth clock having a phase opposite to the third clock, and further functions to pull down a gate signal of at least one odd gate line or at least one even gate line different from the corresponding even gate line.