The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 2013
Filed:
Feb. 11, 2010
Yu-cheng Tsai, Hsinchu, TW;
Kuo-hsien Lee, Hsinchu, TW;
Chao-liang LU, Hsinchu, TW;
Jing-tin Kuo, Hsinchu, TW;
Yu-Cheng Tsai, Hsinchu, TW;
Kuo-Hsien Lee, Hsinchu, TW;
Chao-Liang Lu, Hsinchu, TW;
Jing-Tin Kuo, Hsinchu, TW;
AU Optronics Corporation, Hsinchu, TW;
Abstract
A liquid crystal display (LCD) and methods of driving same. In one embodiment, the LCD) includes a plurality of gate lines, {G}, spatially arranged along a row direction; a plurality of data lines, {D}, spatially arranged along a column direction perpendicular to the row direction, and a plurality of pixels, {P}, spatially arranged in the form of a matrix, where m=1, 2, . . . , M, n=1, 2, . . . , N, and M and N are positive integers. Each pixel Pis defined between two neighboring gate lines Gand Gand two neighboring data lines Dand D, and comprises a first sub-pixel electrode, a second sub-pixel electrode, a first transistor having a gate electrically coupled to the gate line G, a source and a drain electrically coupled to the first sub-pixel electrode, a second transistor having a gate electrically coupled to the gate line G, a source electrically coupled to the source of the first transistor and a drain electrically coupled to the second sub-pixel electrode, and a third transistor having a gate electrically coupled to the gate line G, a source electrically coupled to one of the two neighboring data lines Dand Dand a drain electrically coupled to the sources of the first and second transistors.