The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2013

Filed:

Oct. 22, 2009
Applicants:

Shahin Mehdizad Taleie, San Diego, CA (US);

Jan Paul Van Der Wagt, Carlsbad, CA (US);

Inventors:

Shahin Mehdizad Taleie, San Diego, CA (US);

Jan Paul van der Wagt, Carlsbad, CA (US);

Assignee:

QUALCOMM, Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Techniques for designing a buffer capable of working with low supply voltages, and having active output impedance matching capability to optimize power delivery to a wide range of loads. In an exemplary embodiment, cascode transistors are provided in a buffer architecture employing common-source transistors having unequal width-to-length ratios (W/L) and a resistance having a corresponding fixed ratio to the load. At least one of the cascode transistors may be dynamically biased to minimize a difference between the drain voltages of the common-source transistors. In a further exemplary embodiment, the output impedance of the buffer may be actively tuned by selectively enabling a set of tuning transistors coupled in parallel with the load. Further techniques for providing a calibration mode and an operation mode are described.


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