Testing of an integrated circuit with a plurality of clock domains

Abstract

An integrated circuit comprises a plurality of clock domains (). Test data is shifted into the integrated circuit through a scan chain (). In a test mode a connection is interrupted between a functional output of a first clock domain () and a functional input of a second clock domain (). Test data is applied from the scan chain () to the functional input and a test response is captured into from the functional output. A delay circuit () is used to delay transfer of the test result from the scan cell () to the functional input when the test result is captured in the scan cell (), to ensure that timing differences between the clock domains do not affect the test. Subsequently the test result is shifted through the scan chain.