The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 26, 2013
Filed:
Feb. 03, 2012
Thomas Buechner, Weil im Schoenbuch, DE;
Markus Buehler, Weil im Schoenbuch, DE;
Markus Olbrich, Langenhagen, DE;
Philipp Panitz, Schoenaich, DE;
Lei Wang, Hannover, DE;
Thomas Buechner, Weil im Schoenbuch, DE;
Markus Buehler, Weil im Schoenbuch, DE;
Markus Olbrich, Langenhagen, DE;
Philipp Panitz, Schoenaich, DE;
Lei Wang, Hannover, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method comprises reducing power consumption of an electronic circuit, wherein the electronic circuit comprises at least one logic cone with at least one gate having a single output net, wherein representations of the at least one gate are instances of elements from a standard cell library. Reducing of the power consumption comprises determining an upper bound for dynamic power consumption by calculating transition metrics and power metrics for each gate. Reducing of the power consumption comprises selecting gates with an upper bound for power consumption greater than a predetermined threshold value. For each selected gate, performing operations comprising: testing multiple configurations from the standard cell library for the selected gate by calculating respective upper bound for power consumption for each of the multiple configurations; selecting gate configuration with minimum upper bound for power consumption; and modifying the gate-level design representation according to the selected gate configuration.