Error recover within processing stages of an integrated circuit

Abstract

An integrated circuit includes a plurality of processing stages each including processing logic, a non-delayed signal-capture element, a delayed signal-capture elementand a comparator. The non-delayed signal-capture elementcaptures an output from the processing logicat a non-delayed capture time. At a later delayed capture time, the delayed signal-capture elementalso captures a value from the processing logic. An error detection circuitand error correction circuitdetect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator. The comparatorcompares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.