The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 26, 2013
Filed:
Oct. 11, 2010
Rajeev Sharma, Faridabad, IN;
Ajay Kumar, Darapur Tanda Urmar, IN;
Naresh Dhamija, Greater Noida, IN;
Atul Gupta, Noida, IN;
Ajay K. Gaite, New Delhi, IN;
Llamparidhi L, Bangalore, IN;
Rajeev Sharma, Faridabad, IN;
Ajay Kumar, Darapur Tanda Urmar, IN;
Naresh Dhamija, Greater Noida, IN;
Atul Gupta, Noida, IN;
Ajay K. Gaite, New Delhi, IN;
Llamparidhi l, Bangalore, IN;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method for compensating for variations in timing of data sent to a processor on data bit lines relative to a strobe clock sent to the processor on a strobe clock line that can be used in a dual data rate (DDR) memory identifies discrete minimum and maximum time offset values for test data in selected data bit patterns for the data bit lines. The discrete minimum time offset value is the minimum timing adjustment required to allow the processor to receive the data in a steady-state condition during a data valid window of the strobe clock and the discrete maximum time offset value is a maximum timing adjustment required to allow the processor to receive the data in a steady-state condition during a data valid window of the strobe clock. The discrete minimum and maximum time offset values identify a valid range when the data bit lines supply data in a steady-state condition for latching into the processor by the strobe clock.