The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 26, 2013
Filed:
Feb. 25, 2009
David Theodore Blaauw, Ann Arbor, MI (US);
Dennis Michael Sylvester, Ann Arbor, MI (US);
David Alan Fick, Ann Arbor, MI (US);
Stuart David Biles, Suffolk, GB;
Michael John Wieckowski, Ann Arbor, MI (US);
Scott Mclean Hanson, Farmington Hills, MI (US);
Gregory Kengho Chen, Ann Arbor, MI (US);
David Theodore Blaauw, Ann Arbor, MI (US);
Dennis Michael Sylvester, Ann Arbor, MI (US);
David Alan Fick, Ann Arbor, MI (US);
Stuart David Biles, Suffolk, GB;
Michael John Wieckowski, Ann Arbor, MI (US);
Scott McLean Hanson, Farmington Hills, MI (US);
Gregory Kengho Chen, Ann Arbor, MI (US);
ARM Limited, Cambridge, GB;
The Regents of the University of Michigan, Ann Arbor, MI (US);
Abstract
An apparatus for processing datais provided with a time-to-digital converterwhich serves to measure signal processing delay through one or more signal paths through a processing stage. This measured delay generates a delay value representing a plurality of instances of the signal processing delay which have been measured. Analysis is performed under software control to estimate a worst case signal processing delay through the processing stage based upon the delay values which have been generated. An adjustment of the operating parameters, such as supply voltage and clock frequency, of the apparatus is made to provide a timing margin through the processing stage sufficient to satisfy the worst case signal processing delay which has been estimated without an excessive margin.