The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 26, 2013
Filed:
Mar. 17, 2009
Sheng-chao Liu, Hsin-Chu, TW;
Hsiang-lin Lin, Hsin-Chu, TW;
Kuang-hsiang Liu, Hsin-Chu, TW;
Ching-huan Lin, Hsin-Chu, TW;
Ming-tien Lin, Hsin-Chu, TW;
Sheng-Chao Liu, Hsin-Chu, TW;
Hsiang-Lin Lin, Hsin-Chu, TW;
Kuang-Hsiang Liu, Hsin-Chu, TW;
Ching-Huan Lin, Hsin-Chu, TW;
Ming-Tien Lin, Hsin-Chu, TW;
AU Optronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
A tri-gate pixel structure includes three sub-pixel regions, three gate lines, a data line, three thin film transistors (TFTs), three pixel electrodes, and a common line. The gate lines are disposed along a first direction, and the data line is disposed along a second direction. The TFTs are disposed in the sub-pixel regions respectively, wherein each TFT has a gate electrode electrically connected to a corresponding gate line, a source electrode electrically connected to the data line, and a drain electrode. The three pixel electrodes are disposed in the three sub-pixel regions respectively, and each pixel electrode is electrically connected to the drain electrode of one TFT respectively. The common line crosses the gate lines and partially overlaps the three gate lines, and the common line and the three pixel electrodes are partially overlapped to respectively form three storage capacitors.