Systems, devices and methods for capacitor mismatch error averaging in pipeline analog-to-digital converters

Abstract

Various embodiments of methods and devices for reducing capacitor mismatch errors in a pipeline analog-to-digital converter (ADC) are disclosed, where in a pipeline element circuit and during a first phase, an input voltage provided by a sample-and-hold circuit is presented to first and second capacitors arranged in parallel in the pipeline element circuit. During a second phase, a second voltage corresponding to a second charge associated with the second capacitance is amplified and stored in the pipeline element circuit. During a third phase, the same input voltage of the first phase is again presented to the first and second capacitors, which are arranged in parallel in the pipeline element circuit. During a fourth phase a first voltage corresponding to the first charge is amplified and stored in the pipeline element circuit. After the first, second, third and fourth phases have been completed, digital representations of the first and second voltages are sent though corresponding registers for subsequent averaging along with digital representations of first and second voltages provided by other pipeline element circuits to produce a digital capacitor mismatch error corrected output.