The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8405435 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 26, 2013

Filed:

Nov. 10, 2004
Applicants:

Jonathan Schmitt, Eden Prairie, MN (US);

Roger L. Roisen, Minnetrista, MN (US);

Inventors:

Jonathan Schmitt, Eden Prairie, MN (US);

Roger L. Roisen, Minnetrista, MN (US);

Assignee:

LSI Corporation, Milpitas, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A delay locked loop generates a voltage on a common node as a function of a phase difference between a reference input and a feedback input. A first voltage-controlled delay line coupled between the reference input and the feedback input and has a first delay, which is controlled by the voltage on the common node. A second voltage-controlled delay line is selectively coupled in series with the first delay line, between the reference input and the feedback input, as a function of a test control input. The second delay line has a second delay, which is controlled by the voltage on the common node.


Find Patent Forward Citations

Schmitt, Jonathan. (2013). Delay locked loop having internal test path (U.S. Patent No. 8405435). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8405435

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…