The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 26, 2013
Filed:
Jul. 24, 2008
Torsten Kramer, Wannweil, DE;
Matthias Boehringer, Reutlingen, DE;
Stefan Pinter, Reutlingen, DE;
Hubert Benzel, Pliezhausen, DE;
Matthias Illing, Palo Alto, CA (US);
Frieder Haag, Wannweil, DE;
Simon Ambruster, Wannweil, DE;
Torsten Kramer, Wannweil, DE;
Matthias Boehringer, Reutlingen, DE;
Stefan Pinter, Reutlingen, DE;
Hubert Benzel, Pliezhausen, DE;
Matthias Illing, Palo Alto, CA (US);
Frieder Haag, Wannweil, DE;
Simon Ambruster, Wannweil, DE;
Robert Bosch GmbH, Stuttgart, DE;
Abstract
A production method for chips, in which as many method steps as possible are carried out in the wafer composite, that is, in parallel for a plurality of chips disposed on a wafer. This is a method for producing a plurality of chips whose functionality is implemented on the basis of the surface layer of a substrate. In this method, the surface layer is patterned and at least one cavity is produced below the surface layer, so that the individual chip regions are connected to each other and/or to the rest of the substrate by suspension webs only, and/or so that the individual chip regions are connected to the substrate layer below the cavity via supporting elements in the region of the cavity. The suspension webs and/or supporting elements are cut when the chips are separated. The patterned and undercut surface layer of the substrate is embedded in a plastic mass before the chips are separated.