The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2013
Filed:
Sep. 25, 2011
Zheng Shan, Shenzhen, CN;
Shi-piao Luo, Shenzhen, CN;
Chia-nan Pai, New Taipei, TW;
Shou-kuo Hsu, New Taipei, TW;
Zheng Shan, Shenzhen, CN;
Shi-Piao Luo, Shenzhen, CN;
Chia-Nan Pai, New Taipei, TW;
Shou-Kuo Hsu, New Taipei, TW;
Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Shenzhen, CN;
Hon Hai Precision Industry Co., Ltd., New Taipei, TW;
Abstract
In a method for verifying a printed circuit board (PCB) layout using a computing device, a PCB simulation file is obtained from a storage device of the computing device, and a PCB image is displayed on a display device according to the PCB simulation file. The PCB image includes multiple signal lines and switching voltage regulator nodes (SVRN). A SVRN to be checked is selected from the PCB image, and all signal lines around the SVRN are searched. The method calculates a layout distance between the selected SVRN and each of the searched signal lines, and generates a graphical window interface to position a signal line whose layout distance is equal to or less than the minimum distance. The method further modifies the layout of the positioned signal line to satisfy a layout design specification by increasing the layout distance to the minimum distance.