Array-type processor having delay adjusting circuit for adjusting a clock cycle in accordance with a critical path delay of the data path

Abstract

Disclosed is an array-type processor including a data path unit in which a plurality of processor elements are arranged in an array; a state-transition management unit that stores information for controlling changeover of data paths; and a delay adjusting circuit that adjusts delay of the input clock signal based upon information output from the state-transition management unit, and provides the delay-adjusted clock signal to the data path unit. The delay adjusting circuit has a delay control information memory and a programmable delay. The delay control information memory stores a plurality of items of delay control information, delay control information is read out using a configuration number supplied from the state-transition management unit as an address, and the delay control information is applied to the programmable array. The programmable delay delays the input clock signal by a delay time specified by the delay control information and provides the delayed clock signal to the data path unit.