The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2013

Filed:

Jun. 18, 2010
Applicants:

Sorin Faibish, Newton, MA (US);

John Forecast, Newton Center, MA (US);

Peter Bixby, Westborough, MA (US);

Philippe Armangau, Acton, MA (US);

Sitaram Pawar, Shrewsbury, MA (US);

Inventors:

Sorin Faibish, Newton, MA (US);

John Forecast, Newton Center, MA (US);

Peter Bixby, Westborough, MA (US);

Philippe Armangau, Acton, MA (US);

Sitaram Pawar, Shrewsbury, MA (US);

Assignee:

EMC Corporation, Hopkinton, MA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

Based on a count of the number of dirty pages in a cache memory, the dirty pages are written from the cache memory to a storage array at a rate having a component proportional to the rate of change in the number of dirty pages in the cache memory. For example, a desired flush rate is computed by adding a first term to a second term. The first term is proportional to the rate of change in the number of dirty pages in the cache memory, and the second term is proportional to the number of dirty pages in the cache memory. The rate component has a smoothing effect on incoming I/O bursts and permits cache flushing to occur at a higher rate closer to the maximum storage array throughput without a significant detrimental impact on client application performance.


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