Jitter evaluation

Abstract

A jitter evaluation apparatus for receiving a digital test signal from which a clock signal is recovered, is shown. A clock recovery circuit () recovers a clock signal from the test signal and a synchronization circuit generates a synchronized system clock signal from said recovered clock signal. A sinusoid generator () generates a sinusoid signal from the synchronized system clock signal and a sampling analog to digital converter () samples the sinusoid signal by the recovered clock signal to provide sinusoid samples further comprising: A numerically controlled oscillator () is configured to produce sine values and cosine values in response to receiving an input from the system clock signal and a first multiplier () is configured to produce a first product of the sinusoid samples and the sine values. In addition, a second multiplier is configured to produce a second product of the sinusoid samples and the cosine values. Furthermore, a co-ordinate rotation device () is configured to receive said first product via a first low pass filter () and to receive said second product via a second low pass filter () to produce an output indicative of jitter phase.