Memory device with data prediction based access time acceleration

Abstract

A memory device includes a memory array including a plurality of memory cells, sensing circuitry coupled to at least a given bitline associated with a particular column of the memory cells of the memory array, and access time acceleration circuitry coupled to the bitline. The access time acceleration circuitry is configured to control an amount of time required by the sensing circuitry to access data stored in a given one of the memory cells in the particular column of memory cells, by providing in a current access cycle at least a selected one of a plurality of different supplemental charging and discharging paths for the bitline based at least in part on data accessed using the bitline in a previous access cycle. By way of example, the different supplemental charging and discharging paths may comprise an additional pull-up path configured to supplement operation of a pull-up path of the given memory cell and an additional pull-down path configured to supplement operation of a pull-down path of the given memory cell.