The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2013
Filed:
May. 12, 2010
Chizu Matsumoto, Fujisawa, JP;
Kaname Yamasaki, Higashiyamato, JP;
Michinobu Nakao, Hachioji, JP;
Yoshikazu Saitou, Hamura, JP;
Chizu Matsumoto, Fujisawa, JP;
Kaname Yamasaki, Higashiyamato, JP;
Michinobu Nakao, Hachioji, JP;
Yoshikazu Saitou, Hamura, JP;
Renesas Electronics Corporation, Kawsaki-shi, JP;
Abstract
A repair circuit achieving 'group repair of mixed multiple repair methods' and a repair design method for making a product margin suitable are provided. In a chip mounting multiple RAMs, a repair circuit and a repair design method in consideration of a trade-off of chip yield and area increase along with mounting a repair circuit are provided. A repair circuit achieving 'group repair of mixed multiple repair methods' which can select existence of a repair circuit, and one or more repair methods from I/O, column, and row repairs on the RAMS in the chip, respectively, when a repair circuit is mounted. The repair circuit performs repair per RAM group by sorting the RAMs mounting a repair circuit into a plurality of RAM groups. Also, a repair method which makes a number of acquired good chips in a wafer and an estimation method of the RAM grouping method are provided.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile