The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2013

Filed:

Aug. 31, 2010
Applicants:

Sung-kyu Park, Hwaseong-si, KR;

Tae-sung Park, Cheonan-si, KR;

Kyung-man Kim, Hwaseong-si, KR;

Hye-jin Kim, Suwon-si, KR;

Inventors:

Sung-Kyu Park, Hwaseong-si, KR;

Tae-Sung Park, Cheonan-si, KR;

Kyung-Man Kim, Hwaseong-si, KR;

Hye-Jin Kim, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are a semiconductor package and a method for fabricating the same. The semiconductor package includes a lower package comprising a lower substrate, a lower semiconductor chip mounted on the lower substrate and comprising a redistribution, and a molding layer molding the lower semiconductor chip, an upper package comprising an upper substrate and an upper semiconductor chip mounted on the upper substrate, with the upper package being stacked on the lower package. The semiconductor package further includes an electrical interconnector extending from the upper substrate into the molding layer and connected to the redistribution to electrically connect the upper and lower packages to each other, and a dummy interconnector extending from the upper substrate into the molding layer to physically couple the upper and lower packages to each other.


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