The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2013
Filed:
Jun. 05, 2009
Yongxun Liu, Tsukuba, JP;
Takashi Matsukawa, Tsukuba, JP;
Kazuhiko Endo, Tsukuba, JP;
Shinichi Ouchi, Tsukuba, JP;
Kunihiro Sakamoto, Tsukuba, JP;
Meishoku Masahara, Tsukuba, JP;
Yongxun Liu, Tsukuba, JP;
Takashi Matsukawa, Tsukuba, JP;
Kazuhiko Endo, Tsukuba, JP;
Shinichi Ouchi, Tsukuba, JP;
Kunihiro Sakamoto, Tsukuba, JP;
Meishoku Masahara, Tsukuba, JP;
Abstract
Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing an SOI substrate having a (100) surface orientation, and nano-wire field effect transistor where two triangular columnar members configuring the nano-wires and being made of a silicon crystal layer are arranged one above the other on an SOI substrate having a (100) surface such a way that the ridge lines of the triangular columnar members face via an insulator; processing the silicon crystal configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; and as a nanowire, processing the silicon crystal by orientation dependent wet etching into a shape where two triangular columnar members are arranged one above the other in such a way that the ridge lines of the triangular columnar members configuring the nano-wires face through the ridge lines thereof, and an integrated circuit including the nano-wire field effect transistor.