The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2013
Filed:
Jan. 27, 2010
Lex Kosowsky, San Jose, CA (US);
Bhret Graydon, San Jose, CA (US);
Djabbar Moustafaev, Aptos, CA (US);
Shurui Shang, San Jose, CA (US);
Robert Fleming, San Jose, CA (US);
Lex Kosowsky, San Jose, CA (US);
Bhret Graydon, San Jose, CA (US);
Djabbar Moustafaev, Aptos, CA (US);
Shurui Shang, San Jose, CA (US);
Robert Fleming, San Jose, CA (US);
Shocking Technologies, Inc., San Jose, CA (US);
Abstract
Various aspects provide for incorporating a VSDM into a substrate to create an ESD-protected substrate. In some cases, a VSDM is incorporated in a manner that results in the ESD-protected substrate meeting one or more specifications (e.g., thickness, planarity, and the like) for various subsequent processes or applications. Various aspects provide for designing a substrate (e.g., a PCB) incorporating a VSDM, and adjusting one or more aspects of the substrate to design a balanced, ESD-protected substrate. Certain embodiments include molding a substrate having a VSDM layer into a first shape.