The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 12, 2013
Filed:
Feb. 10, 2006
Applicants:
Paul Ying-fung Wu, Saratoga, CA (US);
Richard L. Wheeler, San Jose, CA (US);
Inventors:
Paul Ying-Fung Wu, Saratoga, CA (US);
Richard L. Wheeler, San Jose, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
An interconnect array uses repeated application of an interconnect pattern ('tile'). The tile has eight I/O signal pins forming a perimeter array, a central pin that can be either a ground pin or an I/O power pin, and an offset ground pin. The I/O signal pins are associated with the same or multiple I/O banks. If the central pin is an I/O power pin, it is optionally associated with an I/O bank associated with one or more of the I/O signal pins.