The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2013

Filed:

Dec. 21, 2010
Applicants:

Fu-yi Tsai, Hsinchu, TW;

Po-chun Hsieh, Kaohsiung, TW;

Wen-ching Hsiung, Hsinchu, TW;

Inventors:

Fu-Yi Tsai, Hsinchu, TW;

Po-Chun Hsieh, Kaohsiung, TW;

Wen-Ching Hsiung, Hsinchu, TW;

Assignee:

Faraday Technology Corp., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01); H01C 7/12 (2006.01); H02H 1/00 (2006.01); H02H 1/04 (2006.01); H02H 3/22 (2006.01);
U.S. Cl.
CPC ...
Abstract

ESD protection circuit with EOS immunity is provided, which includes a first connection circuit, a first EOS control circuit formed by at least a diode, and an ESD clamp respectively coupled between a pad, a first clamp node, an I/O clamp node and a second source node. When the ESD clamp detects ESD through the I/O clamp node, it is triggered to conduct from the I/O clamp node to the second source node. When the pad receives EOS, the first EOS control circuit provides a cross voltage between the first clamp node and the I/O clamp node, such that a voltage of the I/O clamp node becomes less than a characteristic voltage of the ESD clamp to prevent the ESD clamp from reverse conducting.


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