The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2013

Filed:

Sep. 23, 2008
Applicants:

Hsiang-hui Chang, Tapei Hsien, TW;

Bing-yu Hsieh, Taipei, TW;

Jing-hong Conan Zhan, HsinChu, TW;

Inventors:

Hsiang-Hui Chang, Tapei Hsien, TW;

Bing-Yu Hsieh, Taipei, TW;

Jing-Hong Conan Zhan, HsinChu, TW;

Assignee:

Mediatek Inc., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/08 (2006.01); H03C 3/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

Phase error of a time-to-digital converter (TDC) within an all-digital phase-locked loop (ADPLL) is compensated by predicting possible phase error, which are predicted according to an estimated quantization error, a period of a digital-controlled oscillator (DCO), a gain of the TDC or a combination thereof. By appropriate inductions, the possible phase error may be further indicated by the quantization error, a code variance corresponding to a half of a reference period received by a TDC module having the TDC, a dividing ratio of a frequency divider of the ADPLL, a fractional number related to the quantization error or a combination thereof. A digital phase error cancellation module is also used for generating the possible phase error for compensating the phase error of the TDC.


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