The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2013

Filed:

Jul. 08, 2011
Applicants:

Benjamin S. Ting, Saratoga, CA (US);

Peter M. Pani, Mountain View, CA (US);

Inventors:

Benjamin S. Ting, Saratoga, CA (US);

Peter M. Pani, Mountain View, CA (US);

Assignee:

Advantage Logic, Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit having an L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors and (L+2) levels of conductors for L at least equal to one. At least an (i−1)-th level of conductors of the L-PSN comprising Inumber of conductors selectively couple to the i-th level of conductors comprising Inumber of conductors which comprise of D[i] sets of conductors in the L-PSN, where i is selected from [1:L+1], through ((I×D[i])+I) number of switches where each conductor of the Inumber of conductors selectively couples to at least (D[i]+1) number of conductors of the Inumber of conductors, at least one conductor from each of the D[i] sets of conductors, for D[i] greater than one. The integrated circuit can be used in various electronic devices.


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