The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2013

Filed:

Feb. 04, 2010
Applicants:

Masaya Kawano, Kanagawa, JP;

Koji Soejima, Kanagawa, JP;

Nobuaki Takahashi, Kanagawa, JP;

Yoichiro Kurita, Kanagawa, JP;

Masahiro Komuro, Kanagawa, JP;

Satoshi Matsui, Kanagawa, JP;

Inventors:

Masaya Kawano, Kanagawa, JP;

Koji Soejima, Kanagawa, JP;

Nobuaki Takahashi, Kanagawa, JP;

Yoichiro Kurita, Kanagawa, JP;

Masahiro Komuro, Kanagawa, JP;

Satoshi Matsui, Kanagawa, JP;

Assignee:

Renesas Electronics Corporation, Kawasaki-Shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a semiconductor device includes forming an interconnect member, mounting a first semiconductor chip having a semiconductor substrate in a face-down manner on the interconnect member, forming a resin layer on the interconnect member to cover a side surface of the first semiconductor chip, thinning the first semiconductor chip and the resin layer, forming an inorganic insulating layer on a back surface of the first semiconductor chip so as to be in contact with the back surface and to extend over the resin layer, and forming a through electrode so as to penetrate the inorganic insulating layer and the semiconductor substrate.


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