The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 12, 2013
Filed:
Feb. 12, 2010
Junichi Yamada, Kanagawa, JP;
Junichi Yamada, Kanagawa, JP;
Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;
Abstract
A semiconductor integrated circuit includes a group of wirings routed at first to Nth (N being an integer not less than two) wiring positions sequentially arranged in parallel, each of the wirings being divided into two portions comprising a starting end side and a terminating end side; and an Mth buffer circuit that connects the starting end side of the wiring at the Mth wiring position (M being an integer that satisfies 1≦M≦K, wherein K is an integer that satisfies K≦N/2) as an input and the terminating end side of the wiring at the (M+N−K)th wiring position as an output. The group of the wirings has a structure in which connection is switched so that the starting end side of the wiring at a Jth (J being an integer that satisfies K<J≦N) wiring position is routed to the terminating end side of the wiring at a (J−K)th wiring position on a wiring layer above a placement region of the buffer circuit(s). Chip occupying area of the group of wirings and the buffer circuit is reduced.