The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2013

Filed:

Sep. 04, 2007
Applicants:

Pelle Rangsten, Storvreta, SE;

Hakan Johansson, Uppsala, SE;

Johan Bejhed, Uppsala, SE;

Inventors:

Pelle Rangsten, Storvreta, SE;

Hakan Johansson, Uppsala, SE;

Johan Bejhed, Uppsala, SE;

Assignee:

NanoSpace AB, Uppsala, SE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 1/09 (2006.01); H01L 23/48 (2006.01); H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

A wafer assembly () includes a substrate (), in turn including a wafer () or a stack of wafers. The wafer assembly () further includes an electrical connection () arranged through at least a part of the substrate (). The electrical connection () is made by low-resistance silicon. The electrical connection () is positioned in a hole () penetrating at least a part of the substrate (). A surface () of the substrate () confining the hole () is electrically insulating. The electrical connection () has at least one protrusion (), which protrudes transversally to a main extension () of the hole () and the protrusion () protrudes outside a minimum hole diameter (), as projected in the main extension () of the hole (). Preferably, the protrusion () is supported by a support surface () of the substrate (). A manufacturing method is also disclosed.


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