The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2013
Filed:
Jan. 13, 2011
Yanqing Deng, South Burlington, VT (US);
Paul A. Hyde, Essex Junction, VT (US);
James M. Johnson, Milton, VT (US);
Todd G. Mckenzie, Essex Junction, VT (US);
Scott K. Springer, Burlington, VT (US);
Richard Q. Williams, Essex Junction, VT (US);
Yanqing Deng, South Burlington, VT (US);
Paul A. Hyde, Essex Junction, VT (US);
James M. Johnson, Milton, VT (US);
Todd G. McKenzie, Essex Junction, VT (US);
Scott K. Springer, Burlington, VT (US);
Richard Q. Williams, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system and method for developing condensed netlists for sub-circuits within an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists rather than full netlists. An IC layout is segmented into a plurality of sub-circuits, each comprising a group of one or more of a given type of active devices connected to (i.e., sharing) the same electrical sub-circuit terminals through a similar resistive network (i.e. such that they are subjected to approximately the same overall combined parasitic resistances). Full netlists corresponding to the sub-circuits are extracted from the layout and condensed. Each condensed netlist accounts for performance variations (e.g., as a function of variations in operating power supply voltages, operating temperatures and, optionally, self-heating and/or stress) exhibited by the active devices and resistive network in a sub-circuit. The condensed netlists for the sub-circuits are then simulated over the full range of operating temperatures and full range of operating power supply voltages for the integrated circuit in order to generate a performance model for the integrated circuit.