Identifying speed binning test vectors during simulation of an integrated circuit design

Abstract

A method for automated functional coverage includes creating event monitors that monitor signals and events within an IC design based upon timing information in a timing report generated by a timing analysis tool. In particular, speed paths that have a higher timing criticality may be selected for monitoring during simulations of the IC design. In addition, if an event is detected on a speed path, the endpoint of that speed path may be forced to a failing value, and the simulation may be resumed. At some point later in the simulation, the simulation results may be checked to determine if a failure that corresponds to the failing value was observed at a structure that would be visible on a manufactured version of the IC design. If the failure is visible, the test vectors that were used may be identified and captured for use in production testing.