The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2013
Filed:
Dec. 20, 2007
Yuan-sheng Chu, Wugu Township, TW;
Jen-wei Hsieh, Taipei, TW;
Yuan-hao Chang, Tainan, TW;
Tei-wei Kuo, Taipei, TW;
Cheng-chih Yang, Taipei, TW;
Yuan-sheng Chu, Wugu Township, TW;
Jen-wei Hsieh, Taipei, TW;
Yuan-hao Chang, Tainan, TW;
Tei-wei Kuo, Taipei, TW;
Cheng-chih Yang, Taipei, TW;
Genesys Logic, Inc., Shindian, TW;
Abstract
A management method for reducing the utilization rate of random access memory (RAM) while reading data from or writing data to the flash memory is disclosed. A physical memory set is constructed from a plurality of physical memory blocks in the flash memory. A logical set is constructed from a plurality of logical blocks wherein the data stored in the logical set are stored in the physical memory set. Further, the data stored in each of the logical blocks are stored in one number of physical memory blocks. A mapping table is constructed and includes a hash function, a logical set table, a physical memory set table, and a set status table for managing the relationship among the physical memory sets, physical memory blocks, and logical blocks while reading data from or writing data to the flash memory. Further, the management method operates and maintains the physical memory sets, the physical memory blocks, and the logical blocks at a set level so that the utilization rate of random access memory is reduced to decrease the access capacity of the random access memory while operating the physical memory blocks and the logical blocks of the flash memory.