The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2013

Filed:

Aug. 08, 2008
Applicants:

Kenichi Akita, Chigasaki, JP;

Daisuke Okada, Kunitachi, JP;

Keisuke Kuwahara, Fujimino, JP;

Yasufumi Morimoto, Nishinomiya, JP;

Yasuhiro Shimamoto, Tokorozawa, JP;

Kan Yasui, Kodaira, JP;

Tsuyoshi Arigane, Akishima, JP;

Tetsuya Ishimaru, Tokyo, JP;

Inventors:

Kenichi Akita, Chigasaki, JP;

Daisuke Okada, Kunitachi, JP;

Keisuke Kuwahara, Fujimino, JP;

Yasufumi Morimoto, Nishinomiya, JP;

Yasuhiro Shimamoto, Tokorozawa, JP;

Kan Yasui, Kodaira, JP;

Tsuyoshi Arigane, Akishima, JP;

Tetsuya Ishimaru, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
Abstract

A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.


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